The VLSI Front End Design course will give absolute nature of a VLSI system level design with RTL (Register Transfer Level) constructs within it. Module in the course are targeted towards making the learner a fore corner in the fresher’s population socking now beginning or for a professional to exploit now ideas. Laboratory sessions extending beyond Verilog I IDL and VI IDL will make yourself different in competi-tion. The Front End Mine concentrates on logical design pmt. It touches an introductory part of CMOS technology, and more support to understand logical design of combinational circuit, sequential circuits and FSM. Major part of the course content is availed in laboratory sessions with the learning of Verilog HDL and VHDL programming. Synthesis of Rn design modules is mentored to implement it in FPGA & ASIC. Mini-projects and Projects are added to the laboratory work.